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NOT Gate |
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The NOT gate performs the basic
logical function called inversion or complementation. NOT gate is
also called as invertor. The purpose of this gate is to convert one
logic level into the opposite logic level. It has one input and one
output. When a HIGH level is applied to an inverter, A LOW level
appears its output and vice versa. |
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If X is the input, then output F
can be represented mathematically as F = X', Here dot ('). denotes
the NOT (inversion) operation. There are couple other ways to
represent the the inversion, F= !X, here ! represents inversion.
Truth table and symbol of the NOT gate is shown in the figure
below. |
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Symbol |
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Truth
Table |
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NOT gate using
"transistor-resistor" logic is shown in figure below. Where X is
input and F is the output. |
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Circuit |
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When X = 1, The transistor input
pin 1 is HIGH, this produces the forward bias across the emitter
base junction and so the transistor conducts. As the collector
current flows, the voltage drop across RL increases and hence F is
LOW. |
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When X = 0, The transistor input
pin 2 is LOW, this produces no bias voltage across the transistor's
base emitter junction. Thus Voltage at F is HIGH. |
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BUF Gate |
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Buffer or BUF is also a gate, with
exception that, it does not perform any logical operation on its
input. Buffers just pass input to output. Buffers are used to
increase the drive strength or sometime just to introduce delay. We
will look at this in detail later. |
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If X is the input, then output F
can be represented mathematically as F = X. Truth table and symbol
of the Buffer gate is shown in the figure below. |
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Symbol |
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Truth
Table |
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NAND Gate |
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NAND gate is cascade of AND gate
and NOT gate, as shown in figure below. It has two or more inputs
and only one output. The output of NAND gate is HIGH when any one of
its input is LOW (i.e. even if one input is LOW, Output will be
HIGH). |
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NAND From AND and
NOT |
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If X and Y are two inputs, then
output F can be represented mathematically as F = ( X.Y)', Here dot
(.) denotes the AND operation and (') denotes inversion. Truth table
and symbol of the N AND gate is shown in the figure below.
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Symbol |
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Truth
Table |
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X |
Y |
F=(X.Y)' |
0 |
0 |
1 |
0 |
1 |
1 |
1 |
0 |
1 |
1 |
1 |
0
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NOR Gate |
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NOR gate is cascade of OR gate and
NOT gate, as shown in figure below. It has two or more inputs and
only one output. The output of NOR gate is HIGH when any all its
inputs are LOW (i.e. even if one input is HIGH, Output will be
LOW). |
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Symbol |
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If X and Y are two inputs, then
output F can be represented mathematically as F = (X+Y)', Here plus
(+) denotes the OR operation and (') denotes inversion. Truth table
and symbol of the NOR gate is shown in the figure below.
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Truth
Table |
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X |
Y |
F=(X+Y)' |
0 |
0 |
1 |
0 |
1 |
0 |
1 |
0 |
0 |
1 |
1 |
0
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XOR Gate |
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An Exclusive-OR (XOR) gate is gate
with two or three more inputs and one output. The output of a
two-input XOR gate assumes a HIGH state if one and only one input
assumes a HIGH state. This is equivalent to saying that the output
is HIGH if either input X or input Y is HIGH exclusively, and LOW
when both are 1 or 0 simultaneously. |
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If X and Y are two inputs, then
output F can be represented mathematically as F = XY, Here
denotes the XOR operation. XY and is
equivalent to X.Y' + X'.Y. Truth table and symbol of the XOR gate is
shown in the figure below. |
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XOR From Simple
gates |
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Symbol |
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Truth
Table |
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X |
Y |
F=(XY) |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
0 |
1 |
1 |
1 |
0
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XNOR Gate |
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An Exclusive-OR (XOR) gate is gate
with two or three more inputs and one output. The output of a
two-input XOR gate assumes a HIGH state if one and only one input
assumes a HIGH state. This is equivalent to saying that the output
is HIGH if either input X or input Y is HIGH exclusively, and LOW
when both are 1 or 0 simultaneously. |
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If X and Y are two inputs, then
output F can be represented mathematically as F = XY, Here
denotes the XOR operation. XY and is
equivalent to X.Y' + X'.Y. Truth table and symbol of the XOR gate is
shown in the figure below. |
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Symbol |
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Truth
Table |
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X |
Y |
F=(XY)' |
0 |
0 |
1 |
0 |
1 |
0 |
1 |
0 |
0 |
1 |
1 |
1
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